When the performance of a test target device (Electronic Device) such as an LSI (Large Scale Integration), a system LSI, and a SoC (System on Chip) is evaluated, a simulation apparatus has been conventionally used. The simulation apparatus simulates an operation of a test model, which is a modeled version of the test target device, using an ISS (Instruction Set Simulator) (see Japanese Laid-open Patent Publication No. 2004-13227, Japanese Laid-open Patent Publication No. 2006-23852, Japanese Laid-open Patent Publication No. 11-96130, Japanese Laid-open Patent Publication No. 2003-15914, Japanese Laid-open Patent Publication No. 05-158740, and Japanese Laid-open Patent Publication No. 2001-249829).
Specifically, in a conventional technique, hardware of the test model is modeled by Verilog-HDL (Hardware Description Language) at RTL (Register Transfer Level) or SystemC with TLM (Transaction Level Modeling). Regarding software executed on the test model, an execution binary is created by compiling a program described in a C language or an assembly language.
In the conventional technique, by causing the test model to execute the execution binary, the test target device is simulated, and by monitoring each hardware item while the simulation is executed, a simulation result such as a command execution time of the test target device is obtained.
However, a long time is spent for simulating an operation of the test target device in the conventional technique described above.
Specifically, in the conventional technique, complex processing in which the ISS reads the execution binary and executes a command of the execution binary is executed, and hence a long time is spent for simulation on the ISS.
Even when evaluating the performance of the test target device without using the ISS, in the conventional technique, complex processing such as converting the execution binary into a host code is performed (see Japanese Laid-open Patent Publication No. 2004-13227).